Developed during my work as a research associate at the University of Paderborn, ReconOS aims at the investigation and development of a programming and execution model for dynamically reconfigurable hardware devices. These devices, such as Field-Programmable Gate Arrays (FPGAs), are being used more and more in embedded systems but also as accelerators in general purpose computing. Being a rather new technology, dynamically reconfigurable systems are not sufficiently supported by current design methodologies and tools. Especially the unique feature of partial reconfiguration is still difficult to exploit except for hand-crafted designs.
ReconOS extends the multithreaded programming model, already widely established in the software domain, to reconfigurable hardware. Hardware accelerators are no longer confined to the model of a passive coprocessor, being fed with data by the system’s main CPU. Instead, hardware modules within the FPGAs can now actively call operating system functions to interact with other threads in the system, forming a transparent abstraction layer across the HW/SW boundary.
ReconOS is realized as an extension to the existing operating systems eCos and Linux, and is currently pursued as an open source project licensed under the GPL. It has been the basis of my PhD thesis and a number of bachelor’s and master’s theses, and is actively used in the EPiCS project supported by the European Commission’s FP7 programme.
More information about ReconOS can be found on
and in my PhD thesis.