Reducing rSoC synthesis turnaround times with xstcache

Working with complex reconfigurable SoC designs in Xilinx EDK can be a tedious process — especially, when you’re tweaking single VHDL source files of a single pcore, just to have all the pcores resynthesized by a twitchy makefile within the EDK build process. To cut down on design turnaround times, we’ve written a simple Python […]