Reducing rSoC synthesis turnaround times with xstcache

Working with complex reconfigurable SoC designs in Xilinx EDK can be a tedious process — especially, when you’re tweaking single VHDL source files of a single pcore, just to have all the pcores resynthesized by a twitchy makefile within the EDK build process.

To cut down on design turnaround times, we’ve written a simple Python script called xstcache, which does the same what ccache does for C sources. It looks at the input files, synthesis parameters and the environment, and, if the same combination has been used for a previous synthesis run, re-uses the result (the netlist) of that synthesis iteration without actually running XST.

For typical EDK projects, this reduces the time for the syntesis step considerably, as most pcore sources do not change between synthesis iterations.

You can find xstcache at GitHub.

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